ILPGRC: ILP-Based Global Routing Optimization With Cell Movements

The placement and routing steps directly impact the circuit performance, area, power consumption, reliability. To handle high complexity of modern circuits, these are tackled separately by applying a divide-and-conquer approach. Unfortunately, due to continuous increase design rules complexity, convergence solutions can suffer from misalignment, effects an unsatisfactory will be noticed only during when is considered fixed. In this work, we propose ILPGRC, Integer Linear Programming (ILP)-based technique that simultaneously moves cells routes nets optimize Global Routing. ILPGRC enables relocation lead issues without compromising quality concerning number VIAs, wirelength, Design Rule Violations (DRVs). We also partitioning strategy named Checkered paneling, which reduces input size ILP model, making approach scalable. paneling execution multiple models in parallel, providing speedup for large circuits. Additionally, GCell cluster-based legalize solution with minimum disturbance displacement. evaluated our ISPD 2018 2019 Contests circuits within physical synthesis flow composed state-of-the-art place route academic tools. results after detailed show reduce, on average, VIAs 4.69% less than 1% wirelength. DRVs most cases no open left.